Fast & Low - Power Consuming SRAM Design by Fast Precharging Using Equalizer and Sense Circuit

This paper presents a fast and low-power Static Random Access Memory (SRAM) design. SRAM are widely used in computer systems and many portable devices. Proposed SRAM is faster because of precharging at a desired voltage. For the most recent CMOS technologies leakage power dissipation has become a major concern. According to the International Technology Roadmap for Semiconductors (ITRS), leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink. To reduce overall power consumption we have to concern on both static and dynamic power consumption. Firstly, an equalizer with sense circuit was used to precharge bit-lines near voltage (VDD Vt). It reduces both static and dynamic power consumption. Aspect ratio of equalizer is high for fast precharging. Though we are precharging at desired voltage circuit is simpler than conventional SRAM.